Reconfigurable data layout
Source values
C[0:4, 0:4] · fixed input orderOutput buffer
Values keep their identity and color. B0–B15 are banks in one buffer row.
PS · Pass · 00SW · Swap · 1116 ports · 8 stages
Switch commands and model details
| Stage | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
|---|
Routing-only example on the maintained 16-port FP32 BIRRD+ topology. Pass and Swap preserve values; reduction modes are not used. Output port p writes bank p at row 0. The bank grid wraps for display.
Commands are generated and checked with the repository's BIRRD compiler. Fixed wiring also permutes lanes, so all-Pass does not mean identity. The animation slows the transfers for teaching; it is not an RTL timing replay.
Verified switch data · Reconfigurable compute