ASPLOS'26 Tutorial: RAIC
ONE WORKLOAD · TWO 256-PE ARRAYS

Systolic Array vs. FEATHER

See how shape, mapping, and layout affect the work that reaches each PE.

Follow the same operands through a 16×16 systolic array and a 16×16 FEATHER NEST. Start with 7×12×32 (M×K×N), then follow a connected chain whose output becomes the next layer’s input. The seven-row chain also shows a visible producer–consumer layout change.

A transparent teaching model, not a hardware benchmark. The clock counts simplified logical issue, propagation, reduction, and drain steps. Weights are assumed available, memory stalls and actual FP16 pipeline/control delays are not modeled. Compare the assumptions below before reading a cycle difference as an architectural advantage.
01 / MAPPING & COMPUTATION

Same GEMM, different spatial work

16×16 vs. 16×16
Input · #004C99Weight · #006633Partial · #4C0099Result · #990000Unmapped / idle
SYSTOLIC ARRAY

Output-stationary

FEATHER · NEST + BIRRD

Adaptive spatial mapping

02 / PERFORMANCE COMPARISON

Performance comparison by workload

Cycles are modeled logical cycles. PE utilization is useful MACs ÷ (256 × modeled cycles), including fill/drain.

Workload shape
M×K×N
Systolic array (SA)FEATHER

Mapping-dependent gains are not universal. Try the regular control and a weight-stationary or best modeled systolic baseline. Shape alone does not establish that FEATHER outperforms every systolic dataflow.

03 / PRODUCER → CONSUMER

Layout switching is a separate question

Architectural what-if

A producer’s output order may differ from the next mapping’s input order. Watch the same output coordinates change bank/slot assignment below. A matching layout has zero additional repack traffic. Baseline assumptions and any copy cost are explicit, not hidden inside MAC utilization.

Each element keeps its ID and color in both buffers and during transfer. Select an element or click a buffer cell to follow its route.